Current high performance computer system memories include multiple pin VLSI devices and are being architected in increasingly sophisticated manners. To efficiently test these devices, it is necessary to apply large blocks of data to each of the multiple pins of the device
Thorough testing of these devices require that each of the circuits be activated and that a plurality of tests be performed at a rate which will permit high volume testing. Since these devices can contain 100,000 or more logic blocks, and since it may be necessary to test each logic block with a variety of test patterns, a test loop for each of the multiple pins of the device may consist of millions of bits of data. Considering the size of these data requirements in conjunction with the fact that it may be necessary to cycle through a loop multiple times for a given pin, it becomes clear that an efficient way of introducing this data to the device under test is necessary. Current testers consist of processing elements which run at a particular clock cycle as well as memory elements in which the data to be introduced to the device under test is stored. Both the size and the speed of this memory are limiting factors in overall tester performance. Some workers in the field have disclosed methods and apparatus to reduce memory requirements, including methods which utilize data compaction techniques.
Millham, U.S. Pat. No. 4,682,330, discloses a test architecture which reduces memory size by using pin address memories and pin control memories. The Millham architecture has a potential to greatly reduce memory capacity requirements, but does not address speed problems. The tester disclosed in Groves et al., U.S. Pat. No. 4,598,245, compresses the amount of data stored in local test data random access memories for the implementation of a circuit test and thereby reduces the required overall memory capacity. Millham et al., U.S. Pat. No. 4,696,005 discloses a data compaction technique in which only those bits of the data in a random access memory which correspond to data which varies from one test loop to the next is changed from one test loop to the next. This compaction technique also reduces the memory capacity requirements.
Other workers in the tester field have disclosed methods and apparatus for increasing the effective speed of the tester memory. Gillette, U.S. Pat. No. 4,451,918 discloses a tester structure in which multiple hierarchies of memories are used. Data is interleaved to the device under test from two high speed memories, which are in turn provided with interleaved data from four lower speed memories. The result of this interleaving is the ability to introduce data to the device under test at a speed of approximately twice that of the higher speed memory. This technique is similar to the use of a cache memory in a hierarchical memory structure in processors, such as those disclosed in Brickman et al., U.S. Pat. No. 3,806,888, Capozzi, U.S. Pat. No. 4,323,968, and J. P. Liptax, "Structural Aspects of the System B60 Model 85: The Cache," IBM Systems Journal, V7/No. 1, 1968, pp. 15-21. Jeffrey, et. al., U S. Pat. No. 4,931,723 also discloses the use of a cache memory in a tester. In each of these implementations, the preferred data path is through the cache, taking advantage of its higher speed. If the required data is not available in the cache, it must be retrieved from the slower memory, thereby requiring more system clock cycles to fetch the required data. It is for this reason that most cache implementations cannot supply a stream of data at constant speed to the processor or the device under test, as the case may be.
Shimizu, U.S. Pat. No. 4,586,181, provides a tester in which all data elements of a test pattern are stored in the identical addresses of a plurality of memories. The desired test pattern is then generated by addressing the plurality of memories in turn without addressing the same memory successively and by then interleaving the outputs of these memories, thereby increasing system speed. This solution to the problem of limited memory speed requires "n" times the normal memory size with "n" being the number of individual memories. Another tester in which the inputs to the device under test are interleaved is disclosed in Staiter, U.S. Pat. No. 4,389,614. Staiter does not disclose a tester which introduces a string of digital test data to the device under test, but rather a tester in which individual pulses introduced to a device under test are within larger pulse intervals. The pulse intervals are then interleaved so that there is no delay between intervals.
Bogholtz et al., U.S. Pat. No. 4,730,318 also discloses a tester in which memory outputs are interleaved to enhance tester speed. Referring to FIG. 1, control processor 20 provides addresses on line 18 to memory A 15 and commands on line 19 to shift register A 17. The control processor 20 also provides addresses and commands to an identical memory B and shift register B, which are not shown. In response to the commands, shift register A 17 loads the data corresponding to a particular address from memory A 15 over line 72. The output of shift register A 17 on line 71 is interleaved with the other shift register output in multiplexer 16. The combined output on line 21 is then introduced to the device under test.
As shown in the timing diagram in FIG. 1, the address normally steps every four clock cycles at the same time as the data is loaded from memory A 15 on line 72 to shift register A 17. The address is normally presented on line 18 to memory A 15 four clock cycles before the data is loaded into shift register A 17. The data is then shifted one bit at a time over line 71 into multiplexer 16. In FIG. 1 and all subsequent figures, the abbreviation "SR" represents the command "Shift Right." In this manner a successive string of bits corresponding to the data required to be presented to the device under test is outputted from multiplexer 16 on line 21. As can be seen from the timing diagram and the above description, Bogholtz et al. describes an implementation using four bit shift registers. The impact on tester performance of memory speed limitations occurs when the loop being run does not terminate on an address boundary. For example, if the last address transfer of the loop required only one bit of the data presented to the shift register at address 2 time, the control processor 20 would then send the starting address of the next loop to memory A 15 and then one clock cycle later would send a load command over line 19 to shift register A 17. In this situation the tester speed is limited by the memory access time. In normal operation within a loop, the memory has four clock cycles to present the data to the shift register.
None of the currently existing tester configurations address this problem. In prior teachings for enhancing memory performance, a fixed access time for the memory closest to the device under test is assumed, regardless of whether the performance enhancement is achieved by decreasing memory capacity requirements or by increasing effective memory speed.